The speed and performance of modern computer systems continue to advance at an astounding rate. New and improved hardware and software technologies are continually being developed to improve the processing capacities of computers. Usually, such technological advances represent some improvement over previous technologies. Often, however, the new technologies are intended to completely replace the older—rendering them obsolete.
This rapid technological advance creates a number of challenges and problems for computer system designers. Interoperability of systems produced by a wide variety of manufacturers is essential to commercial success. Certain standards for device interfaces and operational protocols must be established and utilized for new technologies. Furthermore, a broad base of existing (or “legacy”) computer systems—utilizing the older, disparate technologies—must be supported to allow end users to migrate to the new technologies without completing replacing their systems every few months. Computer system architects are thus constantly challenged with striking a balance between: extracting optimal performance from new technologies, addressing interoperability requirements, and meeting the needs of legacy system support.
Frequently, such concerns and considerations are addressed through the establishment and observance of industry-wide standards. Various manufacturers and other interested parties collectively determine, for a given technology or technological function, certain required physical and performance parameters. Interoperability and legacy support issues are commonly addressed, as are minimum and maximum performance expectations. Having a standard from which to work, computer system architects may then begin the process of optimizing a particular hardware or software function's design and operation.
Industry standards have been widely relied upon in the design and manufacture a number of computer system components and functions. One particular example is computer bus architectures. Generally speaking, computer bus architectures are concerned with the interface and communication between processing, memory, and input/output system components. One commonly used bus interface is PCI. At the time it was developed, PCI was a very advanced, high-performance parallel bus standard. More recently, a newer bus standard has been developed to more fully utilize new communications technologies (e.g., packet-based, point-to-point). This standard has been called PCI-Express.
Although PCI-X is intended to eventually replace PCI, it must offer legacy support for existing PCI systems and components. Certain PCI protocol communications and operations must be translated into the proper PCI-Express communication or operation, and vice-versa. With a large number of both PCI and PCI-Express system operations communications, the process of translating between the two gives rise to a number of concerns and considerations.
One such consideration is the process of handling interrupt requests, particularly legacy interrupt requests. The PCI standard established an interrupt-processing scheme comprising four physical interrupt signals. Thereafter, a serialized interrupt-processing scheme was developed—serial IRQ. This serialized scheme effectively multiplexed the four PCI interrupt signals for transmission over a single physical interrupt pin.
In general terms, PCI-Express does not rely on a physical interrupt signaling scheme but, rather, on interrupts signaled through messages. This scheme is referred to as message signaled interrupts (MSIs). Although the physical four-interrupt scheme of PCI is not compatible with MSIs, the PCI-Express standard does provide a scheme for mapping these four interrupts into the protocol. This scheme is referred to as INTx virtual wire interrupt signaling. Utilizing this scheme, a device serving as a bridge between a PCI device and a PCI-Express system can successfully map PCI interrupts into the PCI-Express protocol.
Unfortunately, however, there are a large number of PCI products and devices that must, themselves, provide support for even earlier legacy systems and their interrupt schemes. One of the most common such legacy interrupt schemes is ISA. ISA-based systems utilize a dedicated 16-pin physical interrupt scheme. Some currently manufactured PCI products that offer support for dedicated ISA-based interrupts map the 16 ISA interrupt signals, along with the four PCI interrupt signals, into serialized IRQ format via some multiplexing scheme. As it currently exists, however, the PCI-Express standard does not provide any mechanism or scheme for mapping dedicated legacy interrupts, such as ISA-based interrupts, into the PCI-Express protocol. In effect, a PCI-Express based system will not recognize any such dedicated interrupt signals.
As a result, there is a need for a system for signaling serialized interrupts, particularly non-PCI serialized interrupts, using message signaled interrupts from a PCI-Express protocol—providing efficient and robust legacy system support within PCI-Express environments in an easy, cost-effective manner.
The present invention provides a versatile system for signaling non-PCI serialized interrupts in a PCI-Express protocol, using MSIs. The present invention provides, within a PCI-Express bridge device, efficient de-multiplexing and mapping of ISA-based interrupt signals into PCI-Express compatible format. The present invention provides a translation function within the bridge device that monitors Serial IRQ data and, upon assertion of an interrupt, generates an MSI communicating necessary data into the PCI-Express environment. The present invention thus greatly expands legacy system support capabilities within PCI-Express environments in an easy, cost-effective manner, overcoming certain limitations and system incompatibilities associated with conventional methodologies.
More specifically, the present invention provides a method of signaling serialized interrupts within a PCI-Express environment. According to the present invention, a PCI environment is interfaced with a PCI-Express environment. A PCI to PCI-Express bridge device is provided; communicatively linked to the PCI and PCI-Express environments. A translation function is provided within the PCI to PCI-Express bridge device; communicatively linked to the PCI and PCI-Express environments. A serialized interrupt is signaled from within the PCI environment. Based on that serialized interrupt, the translation function then generates a corresponding message signaled interrupt within the PCI-Express environment.
The present invention further provides a PCI-Express to PCI bridge device for translating serialized interrupts into message signaled interrupts. The bridge device comprises a first communicative link with a PCI-Express environment. The bridge device further comprises a second communicative link with a PCI environment. The bridge device also comprises a translation function disposed within the bridge device. The translation function is adapted to identify a serial interrupt signal originating from within the PCI environment, as communicated over the second communicative link. The translation function is further adapted to generate a message signaled interrupt, indicative of the serial interrupt signal, and to transmit that message signaled interrupt into the PCI-Express environment via the first communicative link.
Other features and advantages of the present invention will be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.